1. Field of the Invention
The techniques described herein relate generally to microprocessors, and some embodiments in particular relate to reducing power consumption in a load queue and/or a store queue.
2. Discussion of Related Art
Some superscalar microprocessors are capable of executing instructions out of order to improve performance. However, one concern with executing instructions out of order is that a data hazard can be created when different instructions access the same memory location. For example, if a later instruction is executed out of order prior to an earlier instruction, and both instructions access the same memory location, there is a danger that these instructions may process the wrong data to produce an incorrect result.
To address the potential problems of out of order execution, some superscalar processors implement both a load queue and a store queue. In some implementations, a load queue is a data structure that stores addresses and data for completed load instructions that have retrieved data from memory for use by the microprocessor core. In some implementations, a store queue is another data structure that stores addresses and data for store instructions that transfer data from the microprocessor core to memory. The load queue and store queue may maintain the information about load and store instructions until there is no longer the possibility of a data hazard. The load queue and/or store queue may be implemented in the core of a superscalar microprocessor as dedicated data structures for storing information about load instructions and/or store instructions. In some implementations, the load queue and store queue may each be implemented as a dedicated set of registers.
A load queue and store queue can enable a superscalar processor to perform a variety of techniques for improving performance and avoiding data hazards, including techniques such as store-to-load data forwarding, memory disambiguation, and in-order store retirement. Previously, store-to-load data forwarding and memory disambiguation used fully associative, age-prioritized searches of the store queue or load queue to determine whether these queues had an entry that accessed a particular location in memory.